1. Field of the Invention
The present invention relates to a semiconductor device, and in particular, to a semiconductor device having a plurality of operation modes.
2. Description of the Background Art
In a semiconductor device including a sensor and the like that require initial adjustment, a terminal for mode switching is provided in order to allow switching between a test mode for the initial adjustment and a normal mode for a normal sensing operation from the outside of the semiconductor device. Such a terminal for mode switching is not required after the initial adjustment. Therefore, there is a demand to reduce the number of terminals and to downsize the semiconductor device.
As a technique for reducing the number of terminals in a semiconductor device as described above, Japanese Patent Laying-Open No. 04-039784 (Patent Document 1), for example, discloses a configuration of a microcomputer into which an EPROM storing a program executed by a CPU and data is incorporated and that has, as operation modes, a microcomputer mode where the microcomputer performs a normal operation, a test mode where an operation of the CPU is tested, and an EPROM mode where writing and reading from/to the EPROM is performed. The microcomputer includes: a test/program power supply terminal that has both of a terminal function of switching between the microcomputer mode and the test mode and a terminal function of applying a program voltage for writing to the EPROM, and a control terminal for switching between the test mode and the EPROM mode. The microcomputer mode is selected when the test/program power supply terminal has a first logic level, and the test mode and the EPROM mode are selected when the test/program power supply terminal has a second logic level. Switching between the test mode and the EPROM mode is performed depending on the logic level of the control terminal. Upon switching to the EPROM mode, the program voltage is applied from the test/program power supply terminal.
Furthermore, Japanese Patent Laying-Open No. 01-171036 (Patent Document 2) discloses a configuration of a microcomputer in which a reset terminal is used as a terminal for applying a high-voltage signal for mode switching.
Furthermore, Japanese Patent Laying-Open No. 2008-152621 (Patent Document 3) discloses a configuration of a microcomputer in which a reset terminal is shared by a mode setting signal and a reset signal and an operation mode is specified in accordance with a change in the signal provided to the reset terminal. As a result, it is not necessary to provide a mode setting terminal independently, and the number of terminals in the microcomputer can be reduced.
Furthermore, Japanese Patent Laying-Open No. 05-166391 (Patent Document 4) discloses a configuration in which operation is performed such that, during reading of data, the data is read from a corresponding address of a memory cell array by a read mode signal and an address signal input from an input/output terminal, and the read data is output to the input/output terminal. Operation is performed such that, during writing or rewriting of data, the data from the input/output terminal is written into the corresponding address of the memory cell array by a write mode signal and an address signal input from the input/output terminal. One terminal can serve as a mode control signal input terminal and the input/output terminal, so that the number of terminals is reduced.
Furthermore, Japanese Patent Laying-Open No. 2001-188770 (Patent Document 5) discloses a configuration in which one terminal is shared by a signal line through which a signal is transmitted between an incorporated interface and an external serial memory as well as a corresponding signal line of a bus release request signal line, a bus release acknowledge signal line, an I/O request signal line, and a wait signal line, so that the number of terminals is reduced.
In the configuration disclosed in Patent Document 1, however, a power supply terminal that receives an operating power supply voltage for causing the microcomputer to operate is separately required, in addition to the test/program power supply terminal that receives the program voltage. Eventually, three terminals, that is, the test/program power supply terminal, the control terminal and the power supply terminal are required. Patent Documents 2 to 5 do not disclose a configuration by which such a problem is solved, either.